`timescale 1ns/1ns

module psram_tb;

parameter SYSCLK_PERIOD = 10;

reg SYSCLK;
reg NSYSRESET;

initial
begin
    SYSCLK = 1'b0;
    NSYSRESET = 1'b0;
end

/*iverilog */
initial
begin            
    $dumpfile("wave.vcd");        //生成的vcd文件名称
    $dumpvars(0, psram_tb);    //tb模块名称
end
/*iverilog */
wire psram_clk;
inout [3:0] psram_dio;
wire psram_cs;

assign psram_dio = (psram_u0.psram_state == psram_u0.qpi_read) ? 4'hb:4'hz;
reg [31:0] addr;

reg [31:0] mem_wdata;
reg [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire mem_ready;
reg mem_valid;
initial
begin
    #(SYSCLK_PERIOD * 10 )
        NSYSRESET = 1'b1;
    #1000
        $stop;
end

always @(SYSCLK)
    #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;

reg [3:0] cnt;
always@(posedge SYSCLK or negedge NSYSRESET)begin
    if(!NSYSRESET)begin
        cnt <= 4'h0;
        addr <= 32'h0;
        mem_valid <= 1'b0;
        mem_wdata <= 32'h0;
        mem_wstrb <= 4'd0;
    end
    else if(cnt!=4'hf) begin
        case(cnt)
        4'd0:begin
            mem_wdata <= 32'h112255aa;
            mem_wstrb <= 4'h1;
            mem_valid <= 1'b1;
            addr <= 32'h4;
            cnt <= 4'd0;
            if(mem_ready)begin
                mem_valid <= 1'b0;
                mem_wstrb <= 4'd0;
                mem_wdata <= 32'h0;
                cnt <= 4'd2;
            end
        end
        4'd1:begin
            cnt <= 4'd2;
            addr <= 32'h8;            
        end
        4'd2:begin
            mem_wdata <= 32'h0;
            mem_wstrb <= 4'h0;
            mem_valid <= 1'b1;
            cnt <= 4'd2;
            if(mem_ready)begin
                mem_valid <= 1'b0;
                mem_wstrb <= 4'd0;
                mem_wdata <= mem_rdata + 1'b1;
                cnt <= 4'd3;
            end
        end
        endcase
    end
end
psram psram_u0 (
    .clk(SYSCLK),
    .resetn(NSYSRESET),

    .psram_clk(psram_clk),
    .psram_dio(psram_dio),
    .psram_cs(psram_cs),

    .mem_addr(addr),
    .mem_wdata(mem_wdata),
    .mem_wstrb(mem_wstrb),
    .mem_rdata(mem_rdata),
    .mem_ready(mem_ready),
    .mem_valid(mem_valid)
);

endmodule